(a) Fields of the Invention
The present invention relates to semiconductor devices and their fabrication methods. In particular, the present invention relates to a semiconductor device having a structure in which an insulating film with internal stress covering a gate electrode of a field effect transistor produces stress in a channel region.
(b) Description of Related Art
In recent years, in order to enhance the speed of a semiconductor device, a structure and a method for improving the carrier mobility of the device have been proposed. In these structure and method, a film with internal stress is used to produce stress on a region where carriers flow (a channel region) from the outside, thereby improving the carrier mobility.
FIGS. 17, 18A, and 18B show a conventional semiconductor device having a structure in which an insulating film with internal stress produces stress on a channel region (see, for example, Japanese Unexamined Patent Publication No. 2005-57301). FIG. 17 is a plan view corresponding to the line XVII-XVII in FIGS. 18A and 18B. FIG. 18A is a sectional view corresponding to the line XVIIIa-XVIIIa in FIG. 17, and FIG. 18B is a sectional view corresponding to the line XVIIIb-XVIIIb in FIG. 17.
As shown in FIGS. 17, 18A, and 18B, a semiconductor substrate 100 is formed with an isolation region 101 which defines an active region 100a. Above the active region 100a surrounded with the isolation region 101, a gate electrode 103 having a silicide layer 103a is formed with a gate insulating film 102 interposed therebetween. The side surfaces of the gate electrode 103 and the silicide layer 103a are formed with a side-wall insulating film 113 which is composed of a first sidewall 105 having an L-shaped cross section and a second sidewall 106. Regions of the active region 100a located outside the side-wall insulating film 113 are formed with a source region 107s having a silicide layer 107sa in its top-layer portion and a drain region 108d having a silicide layer 108da in its top-layer portion, respectively. Over the semiconductor substrate 100, a liner film 109 of a silicon nitride film having internal stress is formed to cover the gate electrode 103 and the side-wall insulating film 113. The top of the liner film 109 is formed with an interlayer insulating film 110. The interlayer insulating film 110 is formed with contact plugs 111 penetrating both of the interlayer insulating film 110 and the liner film 109 to reach the silicide layers 107sa and 108da, respectively. The top of the interlayer insulating film 110 is formed with interconnects 112 whose bottom surfaces are connected to the top ends of the contact plugs 111, respectively.
In the conventional semiconductor device thus constructed, as is apparent from FIG. 17, the liner film 109 having internal stress is formed to enclose the gate electrode 103 in the state in which the side-wall insulating film 113 on the side surface of the gate electrode 103 is interposed therebetween.
In this structure, the direction of the channel length in which carriers flow (the channel length direction) is set to the direction in which the source region 107 and the drain region 108 are connected to each other. Then, if the liner film 109 has tensile internal stress, it tends to shrink in its entirety. This applies stress onto the active region 100a, which results in application of tensile stress S1 in the channel length direction of the channel region. For an n-type field effect transistor (an n-type MIS transistor), application of such stress enhances the carrier mobility to increase the current therein, and therefore the semiconductor device can operate at high speed.
For the structure as shown above in which the insulating film with internal stress is formed to enclose the gate electrode, for example, as shown in FIGS. 17 and 18B, the liner film 109 with internal stress also covers an end of a protruding portion of the gate electrode 103 located on the isolation region 101 (referred hereinafter to as “a protrusion of a gate electrode”). Thus, if the liner film 109 with internal stress has tensile internal stress, it tends to shrink in its entirety. In response to this tendency, the protrusion of the gate electrode 103 is compressed in the direction of the channel width that is perpendicular to the channel length direction. This in turn gives compressive stress S2 in the channel width direction of the channel region connected through the gate insulating film 102 to the gate electrode 103.
For a semiconductor element using a (001) substrate and passing carriers in the <110> direction, the channel width direction is the <1-10> direction. Therefore, regardless of whether an n-type MIS transistor using an electron as a carrier or a p-type MIS transistor using a hole as a carrier is employed as the semiconductor element, application of the compressive stress S2 to the channel width direction of the channel region decreases the carrier mobility. As a result, even though the insulating film with internal stress applies tensile stress S1 in the channel length direction of the channel region, the effect of enhancing the carrier mobility provided by the tensile stress S1 is counteracted. Even for a semiconductor element using a (001) substrate and passing carriers in the <100> direction, the effect of enhancing the carrier mobility is counteracted in the same way.
Moreover, as the channel width is smaller, the influence of compressive stress in the channel width direction exerted on the channel region by the protrusion of the gate electrode becomes more significant. As the protrusion of the gate electrode is shorter, the distance from the tip of the protrusion of the gate electrode to the channel region becomes shorter to increase the influence of the compressive stress in the channel width direction exerted on the channel region by the protrusion. These disadvantages are expected to cause problems to future miniaturization of the semiconductor element.